1. Field of the Invention
The invention relates to fabrication of a semiconductor device, and more particularly to fabrication of a CMOS device.
2. Description of the Related Art
To enhance NMOS performance without PMOS degradation in a semiconductor device, CMOS and PMOS devices are typically formed with tensile and compressive stresses, respectively. U.S. Pub. No. 2004/0104405 A1 to Huang et al. describes a CMOS device having at least one PMOS device comprising a first stress layer e.g. a compressive stress layer thereon and at least one NMOS comprising a second stress layer e.g. a tensile stress layer thereon, thus the mobility of holes and electrons within the CMOS device is improved. U.S. Pub. No. 2004/0159834 A1 to Huang et al. describes that adoption of a strained silicon layer facilitates fabrication efficiency of devices. U.S. Pub. No. 2006/0014340 A1 to Hisakazu et al. describes a semiconductor device comprising at least one tensile stress film overlying an NMOS formation region and at least one compressive stress film overlying a PMOS formation region.
With continued shrinkage of integrated circuits, down to 65 nm or below, for example, a local stress technique such as the stress memorization technique (SMT) has been presented to enhance device performance. The article entitled, (SMT) by selectively strained-nitride capping for sub-65 nm high-performance strained-Si device application, by Chien-Hao Chen et al., in VLSI Technology, 2004 presents a stress memorization technique for enhancing device performance. PMOS performance, however, is still degraded. Accordingly, a semiconductor device capable of further improving NMOS performance without PMOS deterioration and fabrication methods thereof are desirable.